The present invention relates to a digital-signal playback apparatus and can be applied to bitabi decoding carried out typically in a video tape recorder and an optical-disc apparatus. By equalizing an input signal on the basis of a result of tentative discrimination of an input signal, limiting the number of possible state transitions of the equalized signal and determining a most probable state transition among the limited number of possible state transitions, it is possible to carry out viterbi decoding on a digital signal by using a simple configuration and, when necessary, at a high speed.
In the conventional playback equipment such a video tape recorder and an optical-disc apparatus, by processing a playback signal by execution of viterbi decoding, a digital signal recorded at a high density can be played back with a high degree of reliability.
In the viterbi decoding, n different states determined by intercode interference are defined by a combination of most recently received input data and, for new incoming input data, the input data is processed by updating the present state into a new state following the present state. To put it concretely, the n different states are determined by immediately preceding (mxe2x88x921) bits where m is the length of the intercode interference. For example, if the input data is 1 and 0 digital data, n different states exist where n=2(mxe2x88x921).
For n different states prescribed as described above, the degree of likelihood of a transition from the present state to a subsequent state is represented by a cumulative value of the squares of differences between an amplitude reference value and an actual playback signal which is accumulated prior to the occurrence of such a state transition. In this case, the distribution of noise included in the playback signal is assumed to be a Gaussian distribution and the amplitude reference value is the value of the playback signal in a state with no noise. Thus, in the viterbi decoding, a cumulative value is computed for each path for which a transition from the present state to one of the n different states is probable and an impending transition is judged to be a transition occurring through a path with the highest degree of likelihood or with a smallest cumulative value. Then, the present state is updated into a new state determined by the path with the highest degree of likelihood and, at the same time, the degree of likelihood of each transition to a further state following the new state and the history of discrimination values are also updated as well for the new state.
If most probable state transitions are sequentially detected one transition after another in this way, at a predetermined stage, pieces of history data of several immediately preceding bits are merged into a single piece of history data, confirming discrimination results obtained so far. In this way, the viterbi encoding identifies a playback signal.
In the viterbi decoding for processing a playback signal as described above, due to the fact that a playback signal can be discriminated by utilizing a signal power of the playback signal at its maximum when noise superposed on the playback signal is random noise, an error rate can be improved in comparison with a decoding system wherein decoding is carried out by comparing the playback signal with a predetermined threshold value for each bit.
FIG. 7 is a table showing state transitions in the case of an application of EPR (Extended Partial Response) 4 equalization to RLL (Run Length Limited) (1, 7) code. It should be noted that the RLL (1, 7) code is code wherein the logic value 1 or 0 appears consecutively at least twice in a row, that is, the logic value 1 or 0 never appears once. This limitation is called d=1 limitation. Thus, the RLL (1, 7) code is code produced by an encoding system based on the d=1 limitation. On the other hand, the EPR4 equalization is a PR (1, 1, xe2x88x921, xe2x88x921) technique wherein, for xe2x80x981xe2x80x99 input data, intercode interference occurs till the bit lagging behind the input data by 3 bits.
Thus, in the application of EPR (Extended Partial Response) 4 equalization to RLL (Run Length Limited) (1, 7) code, a history of previous input data up to the a bit leading ahead of new input data by 3 bits univocally determines a state transition (hence, output data) caused by the new input data following the history of previous input data. For example, let a [k] be new input data and a [k-1], a [k-2] and a [k-3] be pieces of previous input data leading ahead of the input data a [k] by 1 clock, 2 clocks and 3 clocks respectively. A state b [k-1] determined by the pieces of input data a [k-1], a [k-2] and a [k-3] is expressed by a string of the symbol S and values of the pieces of input data a [k-1], a [k-2] and a [k-3]. For example, notation S000 shown in the table of FIG. 7 is the state determined by pieces of input data having values of 0, 0 and 0. As shown in the table, in the state (S000), output data c [k] of 0 is obtained from input data a [k] of 0 and the present state b [k-1] changes from S000 to a next state b [k] of S000.
In the case of RLL (1, 7) code, the states (S010) and (S101) do not exist due to the d=1 limitation described above. Each state b [k-1] can transit to either of 2 states in dependence on whether the input data is 0 or 1. Since preceding 3 bits of input data provide a total of different 8 states, the exclusion of the states (S010) and (S101) leaves only 6 different states. In addition, in the case of RLL (1, 7) code, the output c [k] has 5 different amplitude reference values, namely, xe2x88x922, xe2x88x921, 0, 1 and 2. Transitions among states are expressed by a trellis diagram as shown in FIG. 8.
In the viterbi decoding, the squares (branch metrics) of differences between an EPR4 equalization playback signal and an EPR4 equalization amplitude reference value are accumulated by repeatedly referring to the trellis diagram shown in FIG. 8 and, then, a path that minimizes the cumulative value is selected. Finally, the input signal is decoded.
FIG. 9 is a block diagram showing a playback signal processing system employed in a video tape recorder to which the viterbi decoder of this type is applied. The video tape recorder 1 records and plays back a digital video signal by application of the EPR4 equalization to the RLL (1, 7) code described above. That is to say, an integrating equalizer 2 carries out Nyquist equalization on a playback signal RF generated by a magnetic head to output an analog playback signal RF. A comparison circuit 3 converts a playback signal RF output by the integrating equalizer 2 into binary data, outputting a binary signal S1 as a result of the binary conversion.
A phase comparator 4 compares the phase of a clock signal CK generated by a voltage controlled oscillator (VCO) 5 with the phase of the binary signal S1, outputting a result of the phase comparison to an integrator 6. The integrator 6 imposes a band limit on the result of the phase comparison, outputting an error signal to the voltage controlled oscillator 5. The voltage controlled oscillator 5 generates the clock signal CK by varying the oscillation frequency so that the error signal is sustained at a predetermined level. The phase comparator 4, the voltage controlled oscillator 5 and the integrator 6 constitute a PLL circuit for generating the clock signal CK from the playback signal RF output by the integrating equalizer 2.
An analog-to-digital (A/D) converter 7 converts the analog playback signal RF output by the integrating equalizer 2 by using the clock signal CK as a reference into a digital playback signal DRF as a result of the A/D conversion. A conventional viterbi decoder 8 receives the digital playback signal DRF, discriminating and outputting a binary decoded output D1, a signal to be recorded into a video tape, from the binary decoded output D1.
FIG. 10 is a block diagram showing the conventional viterbi decoder 8. As shown in the figure, the viterbi decoder 8 comprises a branch-metric computing circuit 8A, a branch-metric processing circuit 8B and a path memory unit 8C. The branch metric computing circuit 8A computes branch metrics BM0 [k] to BM4 [k] for the 5 amplitude reference values respectively by execution of processing based on Eq. (1) given below for each sample value of the digital video signal DRF. The branch metrics BM0 [k] to BM4 [k] are each the square of a difference between the level of the actual playback signal sig [k], that is, the digital playback signal DRF, and the value of a playback signal obtained by assuming that no noise exist in a state thereof, that is, the amplitude reference value. As described above, the amplitude reference value can be 1 of 5 values, namely, 2, 1, 0, xe2x88x921 and xe2x88x922. Thus, the branch metrics BM0 [k] to BM4 [k] are each a Euclid distance of the playback signal from an amplitude reference value.
BM0[k]=(sig[k]xe2x88x922)2
BM1[k]=(sig[k]xe2x88x921)2
BM2[k]=(sig[k])2
xe2x80x83BM3[k]=(sig[k]+1)2
BM4[k]=(sig[k]+2)2xe2x80x83xe2x80x83(1)
To put it concretely, the branch metric computing circuit 8A comprises a plurality of systems each including a subtraction circuit for subtracting an amplitude reference value from the digital playback signal DRF, and the same plurality of systems each including a multiplier for finding a square of a result of subtraction produced by the subtraction circuit.
The branch metric processing circuit 8B computes metrics L(S000, k) to L(S111, k) from the branch metrics BM0[k] to BM4[k] computed by the branch metric computing circuit 8A and immediately preceding metrics L(SXXX, k-1) by execution of processing based on Eq. (2) given as follows.
L(S111, k)=min{1(S111, k-1)+BM2[k], L(S011, k-1)+BM1[k]}xe2x80x83xe2x80x83(2-1)
L(S110, k)=min{1(S111, k-1)+BM3[k], L(S011, k-1)+BM2[k]}xe2x80x83xe2x80x83(2-2)
L(S100, k)=L(S110, k-1)+BM4[k]xe2x80x83xe2x80x83(2-3)
L(S011, k)=L(S001, k-1)+BM0[k]xe2x80x83xe2x80x83(2-4)
L(S001, k)=min{1(S100, k-1)+BM2[k], L(S000, k-1)+BM1[k]}xe2x80x83xe2x80x83(2-5)
L(S000, k)=min{L(S100, k-1)+BM3[k], L(S000, k-1)+BM2[k]}xe2x80x83xe2x80x83(2-6)
where notation min(a, b) denotes a function to select the smaller one between the values a and b.
The path memory unit 8C outputs a binary decoded signal D1 based on results of the computation carried out by the branch metric processing circuit 8B.
FIGS. 11 and 12 are block diagrams showing a detailed configuration of the branch metric processing circuit 8B. AS shown in the figures, the branch metric processing circuit 8B comprises metric computing circuits 8BA to 8BF each for computing the metrics L (S111, k) to L (S000, k) of the states (S111) to (S000) respectively.
To put it in detail, in the first metric computing circuit 8BA for computing a metric with respect to a transition to the first state (S111), an adder 10A adds a metric L (S111, k-1), a metric of the first state (S111) computed by the first metric computing circuit 8BA at a time preceding the present time by 1 clock to a branch metric BM2 (k) computed by the branch-metric computing circuit 8A. Thus, the adder 10A produces the first term of the expression on the right-hand side of Eq. (2-1).
An adder 11A adds a metric L (S011, k-1), a metric of the fourth state (S011) computed by the fourth metric computing circuit 8BD at a time preceding the present time by 1 clock to a branch metric BM1 (k) computed by the branch metric computing circuit 8A. Thus, the adder 11A produces a result of addition corresponding to the second term of the expression on the right-hand side of Eq. (2-1).
A comparison circuit 12A compares the data output by the adder 10A with that output by the adder 11A, outputting a result of comparison SEL3. The result of comparison SEL3 output by the comparison circuit 12A is an outcome of formation of a judgment as to whether a transition from the first state (S111) to the first state (S111) or from the fourth state (S011) to the first state (S111) has a higher degree of likelihood, that is, whether a transition from the first state (S111) to the first state (S111) or from the fourth state (S011) to the first state (S111) is more probable.
A selector 13A selects either the result of addition produced by the adder 10A or the result of addition produced by the adder 11A in dependence on the judgment outcome SEL3 output by the comparison circuit 12A. A latch (D) 14A latches an output selected by the selector 13A. Thus, the latch 14A latches and holds the value of the expression on the right-hand side of Eq. (2-1), that is, the final result of the processing carried out by the first metric computing circuit 8BA to represent the metric of the first state (S111).
In the second metric computing circuit 8BB for computing a metric with respect to a transition to the second state (S110), on the other hand, an adder 10B adds a metric L (S111, k-1), a metric of the first state (S111) computed by the first metric computing circuit 8BA at a time preceding the present time by 1 clock to a branch metric BM3 (k) computed by the branch metric computing circuit 8A. Thus, the adder 10B produces the result of addition corresponding to the first term of the expression on the right-hand side of Eq. (2-2).
An adder 11B adds a metric L (S011, k-1), a metric of the fourth state (S011) computed by the fourth metric computing circuit 8BD at a time preceding the present time by 1 clock to a branch metric BM2 (k) computed by the branch metric computing circuit 8A. Thus, the adder 11B produces the result of addition corresponding to the second term of the expression on the right-hand side of Eq. (2-2).
A comparison circuit 12B compares the data output by the adder 10B with that output by the adder 11B, outputting a result of comparison SEL2. The result of comparison SEL2 output by the comparison circuit 12B is an outcome of formation of a judgment as to whether a transition from the first state (S111) to the second state (S110) or from the fourth state (S011) to the second state (S110) has a higher degree of likelihood, that is, whether a transition from the first state (S111) to the second state (S110) or from the fourth state (S011) to the second state (S110) is more probable.
A selector 13B selects either the result of addition produced by the adder 10B or the result of addition produced by the adder 11B in dependence on the judgment outcome SEL2 output by the comparison circuit 12B. A latch (D) 14B latches an output selected by the selector 13B. Thus, the latch 14B latches and holds the value of the expression on the right-hand side of Eq. (2-2), that is, the final result of the processing carried out by the second metric computing circuit 8BB to represent the metric of the second state (S110).
In the third metric computing circuit 8BC for computing a metric with respect to a transition to the third state (S100), on the other hand, an adder 10C adds a metric L (S110, k-1), a metric of the second state (S110) computed by the second metric computing circuit 8BB at a time preceding the present time by 1 clock to a branch metric BM4 (k) computed by the branch metric computing circuit 8A and outputs the result of the addition to a latch (D) 14C for latching the result. Thus, the latch 14C latches and holds the value of the expression on the right-hand side of Eq. (2-3), that is, the result of the processing carried out by the third metric computing circuit 8BC to represent the metric of the third state (S100).
In the fourth metric computing circuit 8BD of FIG. 12 for computing a metric with respect to a transition to the fourth state (S011), on the other hand, an adder 10D adds a metric L (S001, k-1), a metric of the fifth state (S001) computed by the fifth metric computing circuit 8BE at a time preceding the present time by 1 clock to a branch metric BM0 (k) computed by the branch metric computing circuit 8A and outputs the result of the addition to a latch (D) 14D for latching the result. Thus, the latch 14D latches and holds the value of the expression on the right-hand side of Eq. (2-4), that is, the result of the processing carried out by the fourth metric computing circuit 8BD to represent the metric of the fourth state (S011).
In the fifth metric computing circuit 8BE for computing a metric with respect to a transition to the fifth state (S001), on the other hand, an adder 10E adds a metric L (S100, k-1), a metric of the third state (S100) computed by the third metric computing circuit 8BC at a time preceding the present time by 1 clock to a branch metric BM2 (k) computed by the branch metric computing circuit 8A. Thus, the adder 10E produces the first term of the expression on the right-hand side of Eq. (2-5).
An adder 11E adds a metric L (S000, k-1), a metric of the sixth state (S000) computed by the sixth metric computing circuit 8BF at a time preceding the present time by 1 clock to a branch metric BM1 (k) computed by the branch metric computing circuit 8A. Thus, the adder 11E produces the result of addition corresponding to the second term of the expression on the right-hand side of Eq. (2-5).
A comparison circuit 12E compares the data output by the adder 10E with that output by the adder 11E, outputting a result of comparison SEL1. The result of comparison SEL1 output by the comparison circuit 12E is an outcome of formation of a judgment as to whether a transition from the third state (S100) to the fifth state (S001) or from the sixth state (S000) to the fifth state (S001) has a higher degree of likelihood, that is, whether a transition from the third state (S100) to the fifth state (S001) or from the sixth state (S000) to the fifth state (S001) is more probable.
A selector 13E selects either the result of addition produced by the adder 10E or the result of addition produced by the adder 11E in dependence on the judgment outcome SEL1 output by the comparison circuit 12E. A latch (D) 14E latches an output selected by the selector 13E. Thus, the latch 14E latches and holds the value of the expression on the right-hand side of Eq. (2-5), that is, the final result of the processing carried out by the fifth metric computing circuit 8BE to represent the metric of the fifth state (S001).
In the sixth metric computing circuit 8BF for computing a metric with respect to a transition to the sixth state (S000), on the other hand, an adder 10F adds a metric L (S100, k-1), a metric of the third state (S100) computed by the third metric computing circuit 8BC at a time preceding the present time by 1 clock to a branch metric BM3 (k) computed by the branch metric computing circuit 8A. Thus, the adder 10F produces the result of addition corresponding to the first term of the expression on the right-hand side of Eq. (2-6).
An adder 11F adds a metric L (S000, k-1), a metric of the sixth state (S000) computed by the sixth metric computing circuit 8BF at a time preceding the present time by 1 clock to a branch metric BM2 (k) computed by the branch metric computing circuit 8A. Thus, the adder 11F produces the result of addition corresponding to the second term of the expression on the right-hand side of Eq. (2-6).
A comparison circuit 12F compares the data output by the adder 10F with that output by the adder 11F, outputting a result of comparison SEL0. The result of comparison SEL0 output by the comparison circuit 12F is an outcome of formation of a judgment as to whether a transition from the sixth state (S000) to the sixth state (S000) or from the third state (S100) to the sixth state (S000) has a higher degree of likelihood, that is, whether a transition from the sixth state (S000) to the sixth state (S000) or from the third state (S100) to the sixth state (S000) is more probable.
A selector 13F selects either the result of addition produced by the adder 10F or the result of addition produced by the adder 11F in dependence on the judgment outcome SFL0 output by the comparison circuit 12F. A latch (D) 14F latches an output selected by the selector 13F. Thus, the latch 14F latches and holds the value of the expression on the right-hand side of Eq. (2-6), that is, the final result of the processing carried out by the sixth metric computing circuit 8BF to represent the metric of the sixth state (S000).
FIGS. 13, 14 and 15 are block diagrams showing the configuration of the path memory unit 8C. As shown in the figures, the path memory unit 8C comprises 6 path memories 8CA to 8CF for the 6 different states (S111) to (S000) respectively. The path memories 8CA, 8CB, 8CE and 8CF are each a path memory used for inheriting a history (discrimination result) of one of two immediately preceding states in dependence on the judgment result SEL3, SEL2, SEL1 or SEL0 respectively which are output by the metric computing circuits 8BA, 8BB, 8BE or 8BF respectively as described above. 0n the other hand, the path memories 8CC and 8CD are each a path memory for which there is only one history (discrimination result) to be inherited.
FIG. 13 is a block diagram showing a path memory 8CC or 8CD enclosed in a dashed-line block for the third or fourth state (S100) or (S011) respectively for which there is only one history (discrimination result) to be inherited. In the case of the third path memory 8CC, a transition to the third state (S100) thereof occurs through inheritance of the history of the second state (S110) as indicated by the state transitions shown in FIG. 8. A history stored in the third path memory 8CC may then be output to the fifth or sixth path memory 8CE or 8CF for the fifth or sixth state (S001) or (S000) respectively. In addition, data with a fixed value of 0 is supplied to the first latch (D) 16A of the third path memory 8CC in the event of a state transition.
The fourth 8CD path memory for the fourth state (S011) is the same as the third path memory 8CC described above except for the following differences. As shown in FIG. 13, in the first place, a transition to the fourth state (S011) thereof occurs through inheritance of the history of the fifth state (S001) in place of the second state (S110). In the second place, data with a fixed value of 1 instead of 0 is supplied to a latch (D) 16A at the first stage of the fourth path memory 8CD. In the third place, a history stored in the fourth path memory 8CD may be output to the first or second path memory 8CA or 8CB for the first or second state (S111) or (S110) respectively instead of the fifth or sixth path memory 8CE or 8CF for the fifth or sixth state (S001) or (S000). In FIG. 13, the components of the fourth path memory 8CD replacing those of the third path memory 8CC are each enclosed in parentheses after the corresponding component of the third path memory 8CC. In the following description, only the third path memory 8CC is explained. Description of the fourth path memory 8CD is omitted to avoid duplication of explanation.
The third path memory 8CC comprises latches 16A to 16N which constitute a predetermined number of stages. The number of stages is at least equal to the number of bits to be inherited from one path memory to another. Typically, the number of stages is in the range of 16 to 32 bites. The fixed data having a value of 1 and the history held in the second path memory 8CB are latched with timing determined by the clock signal CK. At that time, a binary decoded output D1 is generated from the latch 16N at the last stage.
The first path memory 8CA, one of the remaining path memories 8CA, 8CB, 8CE and 8CF, comprises latches 16A to 16N at as many stages as the third path memory 8CC connected to each other in series as shown in FIG. 14. Between each two adjacent latches of the latches 16A to 16N, a selector 17I where I=A to M is provided. The selectors 17A to 17M each select either a history bit output by the fourth path memory 8CD or the history bit of an immediately preceding latch.
The history bits are selected by the selectors 17A to 17M in accordance with the judgment result SEL3. To put it in detail, when the first metric computing circuit 8BA associated with the first path memory 8CA selects a metric from the fourth state (S011), the judgment result SEL3 drives the selectors 17A to 17M employed in the first path memory 8CA to select history bits from the fourth path memory 8CD. When the first metric computing circuit 8BA selects a metric from the first state (S111) itself, on the other hand, the judgment result SEL3 drives the selectors 17A to 17M employed in the first path memory 8CA to select history bits held by the first path memory 8CA itself. The latch 16A at the first stage always latches fixed data with the value of 1 without regard to these 2 different state transitions. In addition, a binary decoded output D1 is generated from the latch 16N at the last stage.
The sixth path memory 8CF for the sixth state (S000) is the same as the first path memory 8CA described above except for the following differences. As shown in FIG. 14, in the first place, a transition to the sixth state (S000) thereof occurs through selective inheritance of the history of the third path memory 8CC in place of the fourth path memory 8CD. In the second place, data with a fixed value of 0 instead of 1 is supplied to the first latch (D) 16A of the sixth path memory 8CF in the event of inheritance of either history bits. In the third place, a history stored in the sixth path memory 8CF may be output to the fifth or sixth path memory 8CE or 8CF for the fifth or sixth state (S001) or (S000) respectively instead of the first or second path memory 8CA or 8CB for the first or second state (S111) or (S110). In the fourth place, the select signal to drive the selectors 17A to 17M is the judgment result SEL0 instead of SEL3. In FIG. 14, the components of the sixth path memory 8CF replacing those of the first path memory 8CA are each enclosed in parentheses after the corresponding component of the first path memory 8CA. Description of the sixth path memory 8CF is omitted to avoid duplication of explanation.
The second path memory 8CB comprises latches 16A to 16N at as many stages as the third path memory 8CC as shown in FIG. 15. Except the latch 16A at the first stage, the inputs of the latches 16B to 16N are connected to selectors 17A to 17M respectively for selecting either the history of the first path memory 8CA or the history of the fourth path memory 8CD.
The history of the first path memory 8CA or the history of the fourth path memory 8CD is selected by the selectors 17A to 17M in accordance with the judgment result SEL2. To put it in detail, when the second metric computing circuit 8BB associated with the second path memory 8CB selects a metric from the first state (S111), the judgment result SEL2 drives the selectors 17A to 17M employed in the second path memory 8CB to select the history from the first path memory 8CA. When the second metric computing circuit 8BB selects a metric from the fourth state (S011), on the other hand, the judgment result SEL2 drives the selectors 17A to 17M to select the history from the fourth path memory 8CD. The latch 16A at the first stage always latches fixed data with the value of 0 without regard to these 2 different transitions. In addition, a binary decoded output D1 is generated from the latch 16N at the last stage.
The fifth path memory 8CE for the fifth state (S001) is the same as the second path memory 8CB described above except for the following differences. As shown in FIG. 15, in the first place, a transition to the fifth state (S001) thereof occurs through selective inheritance of the history of the sixth or third path memory 8CF or 8CC instead of the history of the first or fourth path memory 8CA or 8CD respectively. In the second place, data with a fixed value of 1 instead of 0 is supplied to the first latch (D) 16A of the fourth path memory 8CD in the event of inheritance of either history. In the third place, a history stored in the fifth path memory 8CE may be output to the fourth path memory 8CD for the fourth state (S011) instead of the third path memory 8CC for the third state (S100). In the fourth place, the select signal to drive the selectors 17A to 17M is the judgment result SEL1 instead of SEL2. In FIG. 15, the components of the fifth path memory 8CE replacing those of the second path memory 8CB are each enclosed in parentheses after the corresponding component of the second path memory 8CA. Description of the fifth path memory 8CE is omitted to avoid duplication of explanation.
In these configurations, when history bits are inherited at the predetermined number of stages, the latches in each of the path memories 8CA to 8CF hold bits of the same history. In the viterbi decoder 8, binary decoded data D1 is output from the latch 16N at the last stage of a path memory selected from the memories 8CA to 8CF.
As described above, in each of the metric computing circuits 8BA to 8BF employed in the viterbi decoder 8, a branch metric BM output by the branch metric computing circuit 8A is added to a metric L [k-1] found previously and, if necessary, results of addition are compared with each other. In accordance with a result of comparison, one of the results of addition is then selected and latched as a metric L [k] computed for input data a [k]. It is necessary to repeat the computation for each clock period of the input data a [k].
As a result, there is raised a problem that it is difficult to apply the conventional viterbi decoder 8 to input data a [k] with high-speed transmission.
In addition, for each state, it is necessary to compute a branch metric BM and a metric L as well as to further store a history, giving rise to another problem of a complex configuration as a whole. As described above, in the case of the EPR4 equalization, processing needs to be carried out for only 6 states. In the case of EEPR4 (PR (1, 2, 0, xe2x88x922, xe2x88x921)), by the way, it is necessary to perform processing for 10 states. As a result, if data must be recorded and transmitted at a high density, the size of the circuit will increase exponentially.
It is thus an object of the present invention addressing the problems described above to provide a digital-signal playback apparatus capable of carrying out viterbi decoding in a simple configuration and a digital-signal playback apparatus capable of carrying out viterbi decoding at a high speed.
In order to solve the problems described above, in the present invention, an input signal is tentatively discriminated at predetermined sampling periods and a binary signal with the same timing as change points of a correct discrimination result or with timing delayed by 1 clock period from the change points of the correct discrimination result is generated. In addition, this input signal is equalized to generate an equalized signal. Further, the number of possible state transitions of the equalized signal is limited on the basis of this binary signal and a most probable state transition is detected from the possible state transitions of the equalized signal which are limited in number to discriminate an input signal.
By tentatively discriminating an input signal at predetermined sampling periods and generating a binary signal with the same change-point timing or with change-point timing delayed by 1 clock period, an input signal can be discriminated by a sufficient discrimination margin even though there is an error of 1 clock with respect to edge timing. In addition, by typically equalizing this input signal if necessary, the discrimination margin can be increased. Furthermore, the number of possible state transitions of the equalized signal can be limited on the basis of this binary signal. By detecting a most probable state transition from the possible state transitions which are limited in number to discriminate an input signal, the most probable state transition can be detected by carrying out less processing due to the reduced number of possible state transitions and the overall configuration can be made simple commensurately. In addition, by limiting the number of possible state transitions, the number of transition paths can also be reduced as well. If necessary, processing to update degrees of likelihood accompanying selection of a state transition can be executed at a period equal to at least 2 sampling periods.